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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. unless otherwise noted, this document contains production data. sn74lvc1g38 sces538e ? january 2004 ? revised august 2017 sn74lvc1g38 single 2-input nand gate with open-drain output 1 1 features 1 ? latch-up performance exceeds 100 ma per jesd 78, class ii ? esd protection exceeds jesd 22 ? 2000-v human-body model (a114-a) ? 200-v machine model (a115-a) ? 1000-v charged-device model (c101) ? available in the texas instruments nanostar ? and nanofree ? packages ? supports 5-v v cc operation ? inputs accept voltages to 5.5 v ? supports down translation to v cc ? maximum t pd of 4.5 ns at 3.3 v ? low power consumption, 10- a maximum i cc ? 24-ma output drive at 3.3 v ? i off supports partial-power-down mode and back- drive protection 2 applications ? av receivers ? blu-ray players and home theaters ? dvd recorders and players ? desktop or notebook pcs ? digital radio or internet radio players ? digital video cameras (dvc) ? embedded pcs ? gps: personal navigation devices ? mobile internet devices ? network projector front-ends ? portable media players ? pro audio mixers ? smoke detectors ? solid state drive (ssd): enterprise ? high-definition (hdtv) ? tablets: enterprise ? audio docks: portable ? dlp front projection systems ? dvr and dvs ? digital picture frame (dpf) ? digital still cameras 3 description the sn74lvc1g38 device is designed for 1.65-v to 5.5-v v cc operation. this device is a single two-input nand buffer gate with open-drain output. it performs the boolean function y = a b or y = a + b in positive logic. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs when the device is powered down. this inhibits current backflow into the device which prevents damage to the device. nanostar ? and nanofree ? package technology is a major breakthrough in ic packaging concepts, using the die as the package. device information (1) device name package body size (nom) SN74LVC1G38DBV sot-23 (5) 2.90 mm 1.60 mm sn74lvc1g38dck sc70 (5) 2.00 mm 1.25 mm sn74lvc1g38dry son (6) 1.45 mm 1.00 mm sn74lvc1g38dsf son (6) 1.00 mm 1.00 mm sn74lvc1g38yzp dsbga (5) 0.89 mm 1.39 mm sn74lvc1g38dpw (2) x2son (5) 0.80 mm 0.80 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. (2) package preview only logic diagram (positive logic) productfolder 1 2 4 a b y support &community tools & software technical documents ordernow
2 sn74lvc1g38 sces538e ? january 2004 ? revised august 2017 www.ti.com product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 6 6.6 switching characteristics, c l = 15 pf ...................... 6 6.7 switching characteristics, c l = 30 pf or 50 pf, ? 40 c to +85 c .......................................................... 6 6.8 switching characteristics, c l = 30 pf or 50 pf, ? 40 c to +125 c ........................................................ 7 6.9 operating characteristics .......................................... 7 6.10 typical characteristics ............................................ 7 7 parameter measurement information .................. 8 8 detailed description ............................................ 10 8.1 overview ................................................................. 10 8.2 functional block diagram ....................................... 10 8.3 feature description ................................................. 10 8.4 device functional modes ........................................ 11 9 application and implementation ........................ 12 9.1 application information ............................................ 12 9.2 typical application ................................................. 12 10 power supply recommendations ..................... 13 11 layout ................................................................... 13 11.1 layout guidelines ................................................. 13 11.2 layout example .................................................... 13 12 device and documentation support ................. 14 12.1 documentation support ........................................ 14 12.2 receiving notification of documentation updates 14 12.3 community resources .......................................... 14 12.4 trademarks ........................................................... 14 12.5 electrostatic discharge caution ............................ 14 12.6 glossary ................................................................ 14 13 mechanical, packaging, and orderable information ........................................................... 14 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision d (december 2013) to revision e page ? added dpw (x2son) package, preview only ....................................................................................................................... 1 ? added applications , device information table, pin configuration and functions section, esd ratings table, thermal information table, typical characteristics , detailed description section, application and implementation section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section .................................................................................................................................................................................... 1 ? added maximum junction temperature, t j ............................................................................................................................. 4 ? changed values in the thermal information table to align with jedec standards ................................................................ 5 changes from revision c (march 2011) to revision d page ? updated document to new ti data sheet format. ................................................................................................................... 1 ? updated i off in features. ......................................................................................................................................................... 1 ? added esd warning. .............................................................................................................................................................. 1 ? updated operating temperature range. .................................................................................................................................. 5
3 sn74lvc1g38 www.ti.com sces538e ? january 2004 ? revised august 2017 product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 5 pin configuration and functions dbv package 5-pin sot-23 top view dck package 5-pin sc70 top view dry package 6-pin son top view nc ? no internal connection. dsf package 6-pin son top view yzp package 5-pin dsbga bottom view see mechanical drawings for dimensions dpw package (1) 5-pin x2son top view (1) preview only pin functions pin i/o description name dbv, dck, dpw dry, dsf yzp a 1 1, 5 a1 i logic input a b 2 2 b1 i logic input b gnd 3 3 c1 ? ground nc ? 5 ? ? no internal connection y 4 4 c2 o output y v cc 5 6 a2 ? positive supply 3 2 4 5 1 a v cc y b gnd 3 2 4 5 1 a v cc y b gnd y v cc b a gnd 1 2 c b a not to scale gnd y b a v cc 6 5 4 2 3 1 b a gnd ncy v cc b nc a 6 5 4 2 3 gnd y v cc 1
4 sn74lvc1g38 sces538e ? january 2004 ? revised august 2017 www.ti.com product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage ? 0.5 6.5 v v i input voltage (2) ? 0.5 6.5 v v o voltage range applied to any output in the high-impedance or power-off state (2) ? 0.5 6.5 v i ik input clamp current v i < 0 ? 50 ma i ok output clamp current v o < 0 ? 50 ma i o continuous output current 50 ma continuous current through v cc or gnd 100 ma t j maximum junction temperature 150 c t stg storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 1000 machine model (mm), a115-a 200
5 sn74lvc1g38 www.ti.com sces538e ? january 2004 ? revised august 2017 product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. see implications of slow or floating cmos inputs , scba004. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage operating 1.65 5.5 v data retention only 1.5 v ih high-level input voltage v cc = 1.65 v to 1.95 v 0.65 v cc v v cc = 2.3 v to 2.7 v 1.7 v cc = 3 v to 3.6 v 2 v cc = 4.5 v to 5.5 v 0.7 v cc v il low-level input voltage v cc = 1.65 v to 1.95 v 0.35 v cc v v cc = 2.3 v to 2.7 v 0.7 v cc = 3 v to 3.6 v 0.8 v cc = 4.5 v to 5.5 v 0.3 v cc v i input voltage 0 5.5 v v o output voltage 0 5.5 v i ol low-level output current v cc = 1.65 v 4 ma v cc = 2.3 v 8 v cc = 3 v 16 24 v cc = 4.5 v 32 t/ v input transition rise and fall rate v cc = 1.8 v 0.15 v, 2.5 v 0.2 v 20 ns/v v cc = 3.3 v 0.3 v 10 v cc = 5 v 0.5 v 5 t a operating free-air temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) sn74lvc1g38 unit dbv (sot-23) dck (sc70) dry (son) dsf (son) yzp (dsbga) dpw (x2son) 5 pins 5 pins 6 pins 6 pins 5 pins 5 pins r ja junction-to-ambient thermal resistance 247.2 276.1 366.9 406.2 146.2 preview c/w r jc(top) junction-to-case (top) thermal resistance 154.5 178.9 253.8 201.0 1.4 preview c/w r jb junction-to-board thermal resistance 86.8 70.9 227.5 256.9 39.3 preview c/w jt junction-to-top characterization parameter 58.0 47.0 75.8 35.2 0.7 preview c/w jb junction-to-board characterization parameter 86.4 69.3 227.7 256.6 39.8 preview c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a n/a n/a n/a n/a preview c/w
6 sn74lvc1g38 sces538e ? january 2004 ? revised august 2017 www.ti.com product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated (1) all typical values are at v cc = 3.3 v, t a = 25 c. 6.5 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ (1) max unit v ol i ol = 100 a t a = ? 40 c to +85 c 1.65 v to 5.5 v 0.1 v t a = ? 40 c to +1255 c i ol = 4 ma t a = ? 40 c to +85 c 1.65 v 0.45 t a = ? 40 c to +1255 c i ol = 8 ma t a = ? 40 c to +85 c 2.3 v 0.3 t a = ? 40 c to +1255 c i ol = 16 ma t a = ? 40 c to +85 c 3 v 0.4 t a = ? 40 c to +1255 c i ol = 24 ma t a = ? 40 c to +85 c 0.55 t a = ? 40 c to +1255 c i ol = 32 ma t a = ? 40 c to +85 c 4.5 v 0.55 t a = ? 40 c to +1255 c i i a or b inputs v i = 5.5 v or gnd t a = ? 40 c to +85 c 1.65 v to 5.5 v 1 a t a = ? 40 c to +1255 c i off v i or v o = 5.5 v t a = ? 40 c to +85 c 0 10 a t a = ? 40 c to +1255 c i cc v i = 5.5 v or gnd, i o = 0 t a = ? 40 c to +85 c 1.65 v to 5.5 v 10 a t a = ? 40 c to +1255 c i cc one input at v cc ? 0.6 v, other inputs at v cc or gnd t a = ? 40 c to +85 c 3 v to 5.5 v 500 a t a = ? 40 c to +1255 c c i v i = v cc or gnd 3.3 v 3.5 pf c o v o = v cc or gnd 3.3 v 4.5 pf 6.6 switching characteristics, c l = 15 pf over recommended operating free-air temperature range, c l = 15 pf (unless otherwise noted) (see figure 2 ) parameter from (input) to (output) test conditions min max unit t pd a or b y t a = ? 40 c to +85 c v cc = 1.8 v 0.15 v 2.9 7.4 ns v cc = 2.5 v 0.2 v 1.7 3.8 v cc = 3.3 v 0.3 v 1.5 4.9 v cc = 5 v 0.5 v 0.9 2.4 6.7 switching characteristics, c l = 30 pf or 50 pf, ? 40 c to +85 c over recommended operating free-air temperature range, c l = 30 pf or 50 pf (unless otherwise noted) (see figure 3 ) parameter from (input) to (output) test conditions min max unit t pd a or b y t a = ? 40 c to +85 c v cc = 1.8 v 0.15 v 2.8 10 ns v cc = 2.5 v 0.2 v 1.6 6 v cc = 3.3 v 0.3 v 1.4 4.5 v cc = 5 v 0.5 v 1 3.9
7 sn74lvc1g38 www.ti.com sces538e ? january 2004 ? revised august 2017 product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 6.8 switching characteristics, c l = 30 pf or 50 pf, ? 40 c to +125 c over recommended operating free-air temperature range, c l = 30 pf or 50 pf (unless otherwise noted) (see figure 3 ) parameter from (input) to (output) test conditions min max unit t pd a or b y t a = ? 40 c to +125 c v cc = 1.8 v 0.15 v 2.8 11 ns v cc = 2.5 v 0.2 v 1.6 6.5 v cc = 3.3 v 0.3 v 1.4 5 v cc = 5 v 0.5 v 1 4.4 6.9 operating characteristics t a = 25 c parameter test conditions typ unit c pd power dissipation capacitance f = 10 mhz v cc = 1.8 v 3 pf v cc = 2.5 v 3 v cc = 3.3 v 4 v cc = 5 v 6 6.10 typical characteristics figure 1. typical i ol vs. v ol (t a = 25 c) i ol (ma) v ol (v) 0 5 10 15 20 25 30 35 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 vol_ v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 5 v
8 sn74lvc1g38 sces538e ? january 2004 ? revised august 2017 www.ti.com product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 7 parameter measurement information (open drain) figure 2. load circuit and voltage waveforms t h t su from output under test c (see note a) l load circuit s1 v load open gnd r l data input timing input 0 v 0 v 0 v t w input 0 v input output waveform 1 s1 at v (see note b) load output waveform 2 s1 at gnd (see note b) v ol v oh 0 v 0 v outputoutput test s1 output control v m v m v m v m v m 1.8 v 0.15 v 2.5 v 0.2 v 3.3 v 0.3 v 5 v 0.5 v 1 m 1 m 1 m 1 m v cc r l 2 v cc 2 v cc 6 v 2 v cc v load c l 15 pf15 pf 15 pf 15 pf 0.15 v 0.15 v 0.3 v 0.3 v v ? 3 v v i v cc /2 v cc /2 1.5 v v cc /2 v m 2 ns 2 ns 2.5 ns 2.5 ns inputs r l t /t r f v cc v cc v cc t (see notes e and f) pzl v load voltage waveforms enable and disable times low- and high-level enabling voltage waveforms propagation delay times inverting and noninverting outputs notes: a. c includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators have the following characteristics: prr 10 mhz, z = 50 . d. the outputs are measured one at a time, with one transition per measurement. e. because this device has open-drain outputs, t and t are the same as t . f. t is measured at v . g. t is measured at v + h. all parameters and waveforms are not applicable to all devices. l o plz pzl pd pzl m plz ol v . ? voltage waveforms pulse duration voltage waveforms setup and hold times v i v i v i v m v m v /2 load t pzl t plz t phz t pzh v C v oh ? v + v ol ? v m v m v m v m v ol v oh v i v i v oh v ol v m v m v m v m t plh t phl t plh t phl t (see notes e and g) plz v load t /t phz pzh v load
9 sn74lvc1g38 www.ti.com sces538e ? january 2004 ? revised august 2017 product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated parameter measurement information (continued) (open drain) figure 3. load circuit and voltage waveforms t h t su from output under test c (see note a) l load circuit s1 v load open gnd r l data input timing input 0 v 0 v 0 v t w input 0 v input output waveform 1 s1 at v (see note b) load output waveform 2 s1 at gnd (see note b) v ol v oh 0 v 0 v outputoutput test s1 output control v m v m v m v m v m 1.8 v 0.15 v 2.5 v 0.2 v 3.3 v 0.3 v 5 v 0.5 v 1 k 500 500 500 v cc r l 2 v cc 2 v cc 6 v 2 v cc v load c l 30 pf30 pf 50 pf 50 pf 0.15 v 0.15 v 0.3 v 0.3 v v ? 3 v v i v cc /2 v cc /2 1.5 v v cc /2 v m 2 ns 2 ns 2.5 ns 2.5 ns inputs r l t /t r f v cc v cc v cc t (see notes e and f) pzl v load voltage waveforms enable and disable times low- and high-level enabling voltage waveforms propagation delay times inverting and noninverting outputs notes: a. c includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators have the following characteristics: prr 10 mhz, z = 50 . d. the outputs are measured one at a time, with one transition per measurement. l o e. because this device has open-drain outputs, t and t are the same as t . f. t is measured at v . g. t is measured at v + v . h. all parameters and waveforms are not applicable to all devices. plz pzl pd pzl m plz ol ? voltage waveforms pulse duration voltage waveforms setup and hold times v i v i v i v m v m v /2 load t pzl t plz t phz t pzh v C v oh ? v + v ol ? v m v m v m v m v ol v oh v i v i v oh v ol v m v m v m v m t plh t phl t plh t phl t (see notes e and g) plz v load t /t phz pzh v load
10 sn74lvc1g38 sces538e ? january 2004 ? revised august 2017 www.ti.com product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 8 detailed description 8.1 overview the sn74lvc1g38 device is designed for 1.65-v to 5.5-v v cc operation. this device is a single two-input nand buffer gate with open-drain output. it performs the boolean function y = a b or y = a + b in positive logic. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs when the device is powered down. this inhibits current backflow into the device which prevents damage to the device. 8.2 functional block diagram figure 4. logic diagram (positive logic) 8.3 feature description 8.3.1 high-drive open-drain output the open-drain output allows the device to sink current when the output is low and maintains a high impedance state when the output is high. the high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. it is important for the power output of the device to be limited to avoid thermal runaway and damage due to over-current. the electrical and thermal limits defined the in the absolute maximum ratings must be followed at all times. 8.3.2 standard cmos inputs standard cmos inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the electrical characteristics . the worst case resistance is calculated with the maximum input voltage, given in the absolute maximum ratings , and the maximum input leakage current, given in the electrical characteristics , using ohm's law (r = v i). signals applied to the inputs need to have fast edge rates, as defined by t/ v in recommended operating conditions to avoid excessive currents and oscillations. if a slow or noisy input signal is required, a device with a schmitt-trigger input should be used to condition the input signal prior to the standard cmos input. 1 2 4 a b y
11 sn74lvc1g38 www.ti.com sces538e ? january 2004 ? revised august 2017 product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated feature description (continued) 8.3.3 clamp diodes the inputs and outputs to this device have negative clamping diodes. caution voltages beyond the values specified in the absolute maximum ratings table can cause damage to the device. the input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. figure 5. electrical placement of clamping diodes for each input and output 8.3.4 partial power down (i off ) the inputs and outputs for this device enter a high impedance state when the supply voltage is 0 v. the maximum leakage into or out of any input or output pin on the device is specified by i off in the . 8.3.5 over-voltage tolerant inputs input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the absolute maximum ratings . 8.3.6 up translation and down translation capable outputs outputs of this device can be driven above the supply voltage so long as they remain below the maximum output voltage value specified in the absolute maximum ratings . when the device is not actively driving low, the output is in the high impedance state. if a pull-up resistor is connected from the output to a power supply (of any valid value), the output will be driven by this supply, and therefore can have a voltage that is either higher or lower than the v cc supply of the device. an application of this device performing up-translation is depicted in application and implementation , where additional design details are provided. 8.4 device functional modes table 1 lists the functional modes of the sn74lvc1g38 device. table 1. function table inputs output y a b l l hi-z l h hi-z h l hi-z h h l gnd logic input output v cc device -i ik -i ok
12 sn74lvc1g38 sces538e ? january 2004 ? revised august 2017 www.ti.com product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information open-drain devices are intrinsically capable of voltage translation. in this application, a 1.8-v logic signal is inverted and up-translated to 5 v at the output when the en signal input is driven high by a 3.3-v signal. the output is held at 5 v in this scenario when the output of the device is in the high impedance state. 9.2 typical application figure 6. gated voltage translating inverter schematic using sn74lvc1g38 9.2.1 design requirements the supply voltage at v 1 must be set to provide input thresholds for the signals a and en. this device uses cmos technology and has an open-drain output. outputs of open-drain devices can be tied directly together to produce a wired-or configuration. this device has high current drive that will create fast edges into light loads so routing and load conditions should be considered to prevent ringing. 9.2.2 detailed design procedure 1. recommended input conditions ? rise time and fall time specs. see ( t/ v) in the recommended operating conditions table. ? specified high and low levels. see (vih and vil) in the recommended operating conditions table. ? inputs are overvoltage tolerant allowing them to go as high as (vi max) in the recommended operating conditions table at any valid vcc. 2. recommended output conditions ? load currents should not exceed (io max). these limits are located in the absolute maximum ratings table. ? outputs can be pulled above vcc for up-translation applications as long as the maximum output voltage in the absolute maximum ratings table is observed. 9.2.3 application curve figure 7. application timing diagram a v 1 v 2 en y r a en y
13 sn74lvc1g38 www.ti.com sces538e ? january 2004 ? revised august 2017 product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 10 power supply recommendations the power supply can be any voltage between the min and max supply voltage rating located in the recommended operating conditions table. the v cc pin should have a good bypass capacitor to prevent power disturbance. it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1- f and 1- f capacitors are commonly used in parallel. the bypass capacitor should be installed as close to the power pin as possible for best results. 11 layout 11.1 layout guidelines when using multiple bit logic devices, inputs should not float. in many cases, functions or parts of functions of digital logic devices are unused. some examples are when only two inputs of a triple-input and gate are used, or when only 3 of the 4-buffer gates are used. such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. specified in figure 8 are rules that must be observed under all circumstances. all unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. the logic level that should be applied to any particular unused input depends on the function of the device. generally they are tied to gnd or v cc , whichever makes more sense or is more convenient. even low data rate digital signals can have high frequency signal components due to fast edge rates. when a printed-circuit board (pcb) trace turns a corner at a 90 angle, a reflection can occur. a reflection occurs primarily because of the change of width of the trace. at the apex of the turn, the trace width increases to 1.414 times the width. this increase upsets the transmission-line characteristics, especially the distributed capacitance and self ? inductance of the trace which results in the reflection. not all pcb traces can be straight and therefore some traces must turn corners. figure 9 shows progressively better techniques of rounding corners. only the last example (best) maintains constant trace width and minimizes reflections. 11.2 layout example figure 8. proper multi-gate input termination diagram figure 9. trace example v cc unused input input output output input unused input worst better best 1w min. w 2w
14 sn74lvc1g38 sces538e ? january 2004 ? revised august 2017 www.ti.com product folder links: sn74lvc1g38 submit documentation feedback copyright ? 2004 ? 2017, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation see the following: implications of slow or floating cmos inputs , scba004 12.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks nanostar, nanofree, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 12.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 18-aug-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples psn74lvc1g38dpwr active x2son dpw 5 3000 tbd call ti call ti -40 to 125 SN74LVC1G38DBVr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (c385, c38f, c38r) (c38h, c38p, c38s) SN74LVC1G38DBVre4 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (c385, c38f, c38r) (c38h, c38p, c38s) SN74LVC1G38DBVt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (c385, c38r) (c38h, c38s) sn74lvc1g38dckr active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (d75, d7f, d7r) (d7h, d7p, d7s) sn74lvc1g38dckrg4 active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (d75, d7f, d7r) (d7h, d7p, d7s) sn74lvc1g38dckt active sc70 dck 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (d75, d7r) (d7h, d7s) sn74lvc1g38dryr active son dry 6 5000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 d7 sn74lvc1g38dsfr active son dsf 6 5000 green (rohs & no sb/br) cu nipdau | cu nipdauag level-1-260c-unlim -40 to 125 d7 sn74lvc1g38yzpr active dsbga yzp 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 d7n (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption.
package option addendum www.ti.com 18-aug-2017 addendum-page 2 green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant SN74LVC1G38DBVr sot-23 dbv 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 SN74LVC1G38DBVr sot-23 dbv 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 q3 SN74LVC1G38DBVt sot-23 dbv 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 q3 sn74lvc1g38dckr sc70 dck 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74lvc1g38dckt sc70 dck 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74lvc1g38dryr son dry 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 q1 sn74lvc1g38dsfr son dsf 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 sn74lvc1g38yzpr dsbga yzp 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 q1 package materials information www.ti.com 3-aug-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) SN74LVC1G38DBVr sot-23 dbv 5 3000 202.0 201.0 28.0 SN74LVC1G38DBVr sot-23 dbv 5 3000 180.0 180.0 18.0 SN74LVC1G38DBVt sot-23 dbv 5 250 180.0 180.0 18.0 sn74lvc1g38dckr sc70 dck 5 3000 180.0 180.0 18.0 sn74lvc1g38dckt sc70 dck 5 250 180.0 180.0 18.0 sn74lvc1g38dryr son dry 6 5000 184.0 184.0 19.0 sn74lvc1g38dsfr son dsf 6 5000 184.0 184.0 19.0 sn74lvc1g38yzpr dsbga yzp 5 3000 220.0 220.0 35.0 package materials information www.ti.com 3-aug-2017 pack materials-page 2
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